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IRS20955(S)PbF
VDD
Vth1
`
COMP1
Ct
CSD
Vth2
`
COMP2
OC
S
R
Q
UVLO(VB)
OC DET (H)
VSS
HV
LEVEL
SHIFT
FLOATING INPUT
HV
LEVEL
SHIFT
HV
LEVEL
SHIFT
FLOATING HIGH SIDE
LOW SIDE
OC DET (L)
UVLO(VCC)
SD
PWM
DEAD TIME
`
HO
LO
Figure 7. Shutdown Functional Block Diagram
Designing C t
Protection Control
The internal protection control block dictates the
operational mode-normal, or shutdown, using the
input of the CSD pin. The IC functions as expected
in the normal mode. In shutdown mode, the IC
forces LO and HO to output 0 V with respect to
COM and VS to turn off the power MOSFETs.
The timing capacitor, C t , is used to program t RESET
and t SU .
? t RESET, is the amount of time that elapses
from when the IC enters shutdown mode to
the time when the IC resumes operation.
t RESET should be long enough to avoid over
heating the MOSFET from the repetitive
sequence of shutting down and resuming
The CSD pin provides five functions.
1. Power up delay timer
2. Self-reset timer
3. Shutdown input
4. Latched protection configuration
5. Shutdown status output (host I/F)
?
operation during over-current conditions. In
most of applications, the minimum
recommended time for t RESET is 0.1.
t SU is the amount of time between powering
up the IC in shutdown mode to the moment
the IC releases shutdown to begin normal
operation.
Self Reset Protection
The values chosen for t RESET and t SU will determine
the capacitance of C t using the given equations:
By putting a capacitor between CSD and VSS, the
IRS20955S can reset itself after entering shutdown
mode.
C t =
t RESET ? I CSD
1 . 1 ? V DD
[F]
Ct
VDD
CSD
IN
VSS
CSH
VB
HO
VS
C t =
t SU ? I CSD
0 . 7 ? V DD
[F]
NC
NC
VREF
OCSET
DT
VCC
LO
COM
where I CSD = the charge/discharge current at the
CSD pin
Figure 8. Self Reset Protection Configuration
www.irf.com
V DD = the supply voltage with respect to V SS.
10
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